1. Field of the Invention
The present invention relates to a cavity-down chip package, and more particularly to a cavity-down multiple-chip package without enlarging the size of the circuit substrate.
2. Description of the Related Art
As electronic products gradually become thinner and lighter, the chips or the micro-electronic element comprising chips are not only reduced in volume, but also further densely packaged into a multiple-chip package. Thus, the multiple-chip package will generate a higher temperature during operation. Furthermore, the multiple-chip package is usually appropriately modified depending on the configuration of the package, resulting in an enlarged size of the circuit substrate, and accordingly deteriorated overall heat spreading effects.
A conventional configuration of the chip package is a Cavity-Down Ball Grid Array package, wherein a heat spreader is attached to a substrate with an opening, so as to form a chip carrier with a cavity facing downwards. At least one chip is accommodated within said opening and attached to the heat spreader, so as to enhance the heat spreading effects.
Referring to FIG. 1, a cavity-down multiple-chip package 100 comprises a heat spreader 110 and a circuit substrate 120. The circuit substrate 120 comprises an upper surface 121 and a lower surface 122. The heat spreader 110 is attached to the upper surface 121 of the circuit substrate 120. A cavity is formed by an opening 123 of the circuit substrate 120 and the heat spreader 110, and is used for accommodating a plurality of chips 130. The chips 130 are attached to the heat spreader 110 to enhance the heat spreading effects. A plurality of solder pads 131 of the chips 130 are connected to a plurality of connecting pads 124 of the circuit substrates 120 by a plurality of bonding wires 140, such that the chips 130 are electrically connected to the circuit substrate 120. A molding compound 150 is formed within the cavity, for sealing the chips 130 and the bonding wires 140. A plurality of ball pads 125 are formed on the lower surface 122 of the circuit substrate 120, and are used for being disposed with a plurality of solder balls 160. Since the chips 130 of the cavity-down multiple-chip package 100 are adhered to the heat spreader 110 on the same plane, the sizes of the circuit substrate 120 and the opening 123 must be enlarged in order to accommodate the chips 130, which in turn accordingly enlarge the footprint of the cavity-down multiple-chip package 100 jointed to a printed circuit board. Therefore, such a conventional configuration is unsuitable for electronic products with small volumes.
ROC (Taiwan) Patent Publication No. 577153, entitled “Cavity-Down Multiple-Chip Package”, discloses a cavity-down multiple-chip package. A cavity is defined by a heat spreader connected with a substrate with an opening; a carrier board for line redistribution and transmission is disposed on the heat spreader and accommodated within the cavity, for being disposed with a plurality of semiconductor chips. These semiconductor chips do not directly contact the heat spreader, thus the heat spreading effect is poor. In addition, since the carrier board for line redistribution and transmission is accommodated within the cavity, the sizes of the cavity and the substrate must be enlarged, such that the footprint of the cavity-down multiple-chip package is enlarged accordingly.
Consequently, there is an existing need for a cavity-down multiple-chip package to solve the above-mentioned problems.